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21-S3-C830A/P830A-032002
USER'S MANUAL
S3C830A/P830A 8-Bit CMOS Microcontroller Revision 1
S3C830A/P830A
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.
S3C830A MICROCONTROLLER
The S3C830A single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce power consumption. The S3C830A is a microcontroller with a 48K-byte mask-programmable ROM embedded. The S3P830A is a microcontroller with a 48K-byte one-time-programmable ROM embedded. Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC CPU core: -- Large number of programable I/O ports (Total 72 pins) -- PLL frequency synthesizer -- 16-bits intermediate frequency counter -- Two synchronous SIO modules -- Two 8-bit timer/counters -- One 16-bit timer/counter -- Low voltage reset -- A/D converter with 4 selectable input pins
OTP
The S3C830A microcontroller is also available in OTP (One Time Programmable) version, S3P830A. The S3P830A microcontroller has an on-chip 48K-byte one-time-programmable EPROM instead of masked ROM. The S3P830A is comparable to S3C830A, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C830A/P830A
FEATURES
CPU * SAM88RC CPU core Two 8-bit Serial I/O Interface * * * 8-bit transmit/receive mode 8-bit receive mode Selectable baud rate or external clock source
Memory * * 2064-byte internal register file (including LCD display RAM) 48K-byte internal program memory area
PLL Frequency Synthesizer * VIN level: 300mVpp (minimum) * * AMVCO range: 0.5 MHz-30 MHz FMVCO range: 30 MHz-150 MHz
Instruction Set * * 78 instructions Idle and Stop instructions
72 I/O Pins * * 32 normal I/O pins 40 pins sharing with LCD segment signals
16-Bit Intermediate Frequency (IF) Counter * VIN level: 300mVpp (minimum) * * AMIF range: 100 kHz-1 MHz FMIF range: 5 MHz-15 MHz
Interrupts * * 8 interrupt levels and 17 internal sources Fast interrupt processing feature
LCD Controller/Driver * * * 40 segments and 4 common terminals 4/3/2 common and static selectable Internal or external resistor circuit for LCD bias
8-Bit Basic Timer * * Watchdog timer function 4 kinds of clock source
Low Voltage Reset (LVR) * * Low voltage check to make system reset VLVR: 3.5 V (typical)
Timer/Counter 0 * * * Programmable 8-bit internal timer External event counter function PWM and capture function
Two Power-Down Modes * * Idle mode: only CPU clock stops Stop mode: system clock and CPU clock stop
Timer/Counter 1 * * Programmable 8-bit interval timer External event counter function
Oscillation Source * Crystal or ceramic for system clock (fx)
Instruction Execution Time * 890 ns at 4.5 MHz (minimum)
Timer/Counter 2 * * Programmable 16-bit interval timer External event counter function
Operating Temperature Range * -25 C to +85 C
Watch Timer * * Interval Time: 50ms, 0.5s, 1.0s at 4.5 MHz 1/1.5/3/6 kHz buzzer output selectable
Operating Voltage Range * * 3.0 V to 5.5 V at 0.4 MHz-4.5 MHz 4.5 V to 5.5 V in PLL/IFC block
Analog to Digital Converter * * 4-channel analog input 8-bit conversion resolution Package Type * 100-pin QFP package
1-2
S3C830A/P830A
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.0-P1.7/ RESET INT0-INT7 XIN XOUT P0.2/T0CAP P0.1/T0CLK P0.3/T0OUT/T0PWM P0.4/T1CLK P0.5/T1OUT P0.6/T2CLK P0.7/T2OUT P3.1/SCK0 P3.2/SO0 P3.3/SI0 P3.4/SCK1 P3.5/SO1 P3.6/SI1 Watchdog Timer P3.0/BUZ COM0-3 P8.7-P4.0/SEG0-39 BIAS VLC0-VLC2 VCOAM VCOFM EO0/EO1 AMIF FMIF P2.0-P2.3/AD0-AD3
CE P0.0 P0.1/T0CLK P0.2/T0CAP P0.3/T0OUT/T0PWM P0.4/T1CLK P0.5/T1OUT P0.6/T2CLK P0.7/T2OUT P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 P1.7/INT7 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4 P2.5 P2.6 P2.7 P3.0/BUZ P3.1/SCK0 P3.2/SO0 P3.3/SI0 P3.4/SCK1 P3.5/SO1 P3.6/SI1 P3.7 P4.0/SEG39 P4.1/SEG38 P4.2/SEG37 P4.3/SEG36 P4.4/SEG35 P4.5/SEG34 P4.6/SEG33 P4.7/SEG32 P5.0/SEG31 P5.1/SEG30 P5.2/SEG29 P5.3/SEG28 P5.4/SEG27 P5.5/SEG26 P5.6/SEG25 P5.7/SEG24 P6.0/SEG23 P6.1/SEG22 P6.2/SEG21 P6.3/SEG20 P6.4/SEG19 P6.5/SEG18 P6.6/SEG17 P6.7/SEG16 P7.0/SEG15 P7.1/SEG14 P7.2/SEG13 P7.3/SEG12 P7.4/SEG11 P7.5/SEG10 P7.6/SEG9 P7.7/SEG8
OSC 8-Bit Timer/ Counter0 8-Bit Timer/ Counter1 Port 1 16-Bit Timer/ Counter2 SIO 0 Port 2 SIO 1 Port 0
I/O Port and Interrupt Control
Basic Timer Port 3 Watch Timer LCD Driver/ Controller Port 4 PLL Synthesizer IF Counter Port 5 8-Bit ADC
SAM88RC Core
AVDD P8.0/SEG7 P8.1/SEG6 P8.2/SEG5 P8.3/SEG4 P8.4/SEG3 P8.5/SEG2 P8.6/SEG1 P8.7/SEG0 LVREN
48K-byte ROM
2064-byte Register File
Port 6
Port 8
Port 7 Low Voltage Reset TEST1 TEST3 VDD VSS TEST2 VDDPLL0 VSSPLL VDDPLL1
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C830A/P830A
PIN ASSIGNMENT
FMIF VDDPLL0 EO0 EO1 CE P0.0 P0.1/T0CLK P0.2/T0CAP P0.3/T0OUT/T0PWM P0.4/T1CLK P0.5/T1OUT P0.6/T2CLK P0.7/T2OUT P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
P1.7/INT7 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4 P2.5 P2.6 P2.7 AVDD P3.0/BUZ P3.1/SCK0 P3.2/SO0 P3.3/SI0 VDD VSS XOUT XIN TEST1 TEST2 P3.4/SCK1 RESET P3.5/SO1 P3.6/SI1 P3.7 P4.0/SEG39 P4.1/SEG38 P4.2/SEG37 P4.3/SEG36 P4.4/SEG35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3C830A
100-QFP-1420C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
AMIF VSSPLL VCOAM VCOFM VDDPLL1 LVREN TEST3 BIAS VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 SEG0/P8.7 SEG1/P8.6 SEG2/P8.5 SEG3/P8.4 SEG4/P8.3 SEG5/P8.2 SEG6/P8.1 SEG7/P8.0 SEG8/P7.7 SEG9/P7.6 SEG10/P7.5 SEG11/P7.4 SEG12/P7.3 SEG13/P7.2 SEG14/P7.1
Figure 1-2. S3C830A Pin Assignments (100-QFP)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG15/P7.0 SEG16/P6.7 SEG17/P6.6 SEG18/P6.5 SEG19/P6.4 SEG20/P6.3 SEG21/P6.2 SEG22/P6.1 SEG23/P6.0 SEG24/P5.7 SEG25/P5.6 SEG26/P5.5 SEG27/P5.4 SEG28/P5.3 SEG29/P5.2 SEG30/P5.1 SEG31/P5.0 SEG32/P4.7 SEG33/P4.6 SEG34/P4.5
1-4
S3C830A/P830A
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C830A Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0-P1.7 Pin Type I/O Pin Description I/O port with bit programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Circuit Type E-4 Pin No. 86 87 88 89 90 91 92 93 94-1 Share Pins - T0CLK T0CAP T0OUT/T0PWM T1CLK TOUT T2CLK T2OUT INT0-INT7
I/O
I/O port with bit programmable pins; Schmitt trigger Input or push-pull output and software assignable pull-ups; Alternately used for external interrupt input (noise filters, interrupt enable and pending control). I/O port with bit programmable pins; Schmitt trigger input or push-pull output and software assignable pull-ups. I/O port with bit programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
D-7
P2.0-P2.3 P2.4-P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0-P4.7
I/O
F-16 D-4 E-4
2-5 6-9 11 12 13 14 21 23 24 25 26-33
AD0-AD3 - BUZ SCLK0 SO0 SI0 SCK1 SO1 SI1 - SEG39-SEG32
I/O
I/O
I/O port with nibble programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. I/O port with nibble programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. I/O port with nibble programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. I/O port with nibble programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. I/O port with nibble programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
H-41
P5.0-P5.7
I/O
H-41
34-41
SEG31-SEG24
P6.0-P6.7
I/O
H-41
42-49
SEG23-SEG16
P7.0-P7.7
I/O
H-41
50-57
SEG15-SEG8
P8.0-P8.7
I/O
H-41
58-65
SEG7-SEG0
1-5
PRODUCT OVERVIEW
S3C830A/P830A
Table 1-1. S3C830A Pin Descriptions (Continued) Pin Names COM0-COM3 SEG0-SEG39 BIAS VLC0 VLC1 VLC2 VDD VSS VDDPLL0-1 VSSPLL AVDD XOUT, XIN TEST1, TEST2 TEST3 LVREN RESET CE Pin Type O I/O I I Pin Description Common signal output for LCD display LCD segment signal output LCD power control LCD power supply Voltage dividing resistors are assignable by software Main power supply Main ground PLL/IFC power supply PLL/IFC ground A/D converter power supply Main oscillator pins for CPU oscillation Test signal input pin (Must be connected to VSS) Test signal output pin (Must be remained to open) LVR enable pin (Must be connected to VDD or VSS) System reset pin Input pin for checking device power Normal operation is high level and PLL/IFC Operation is stopped at low power PLL's phase error output0 PLL's phase error output1 External VCOAM/VCOFM signal inputs Circuit Type H H-41 - - Pin No. 69-66 65-26 73 72-70 Share Pins - P8-P4 - -
- - - - - - I O I I I
- - - - - - - - A B B-5
15 16 82, 76 79 10 17, 18 19, 20 74 75 22 85
- - - - - - - - - - -
EO0 EO1 VCOAM VCOFM
O O I
A-2 A-2 B-4
83 84 78, 77
- - -
1-6
S3C830A/P830A
PRODUCT OVERVIEW
Table 1-1. S3C830A Pin Descriptions (Continued) Pin Names FMIF, AMIF AD0-AD3 BUZ SCK0 SO0 SI0 SCK1 SO1 SI1 T0CLK T0CAP T0OUT T0PWM T1CLK T1OUT T2CLK T2OUT INT0-INT7 Pin Type I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ADC input pins 1, 1.5, 3 or 6 kHz frequency output for buzzer sound at 4.5 MHz clock SIO0 interface signal SIO0 interface data output signal SIO0 interface data input signal SIO1 interface signal SIO1 interface data output signal SIO1 interface data input signal Timer 0 clock input Timer 0 capture input Timer 0 clock output Timer 0 PWM output Timer 1 clock input Timer 1 clock output Timer 2 clock input Timer 2 clock output External interrupt input pins Pin Description FM/AM intermediate frequency signal inputs Circuit Type B-4 F-16 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 E-4 D-7 Pin No. 81, 80 2-5 11 12 13 14 21 23 24 87 88 89 89 90 91 92 93 94-1 Share Pins - P2.0-P2.3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P0.1 P0.2 P0.3 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0-P1.7
1-7
PRODUCT OVERVIEW
S3C830A/P830A
PIN CIRCUITS
VDD In P-Channel In N-Channel N-CH Type A Feedback Enable Pull-down Enable
Figure 1-3. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B-4
VDD
Up
P-Channel Out In
Down
N-Channel
Figure 1-4. Pin Circuit Type A-2 (EO)
Figure 1-7. Pin Circuit Type B-5 (CE)
VDD Pull-up Resistor
VDD
Data
P-Channel Out
In Schmitt Trigger
Output Disable
N-Channel
Figure 1-5. Pin Circuit Type B (RESET RESET)
Figure 1-8. Pin Circuit Type C
1-8
S3C830A/P830A
PRODUCT OVERVIEW
VDD
VDD Open-Drain Enable VDD Pull-up Resistor Pull-up Enable P-CH Data I/O N-CH Output Disable VSS
Pull-up Enable Data Output Disable Circuit Type C I/O
ADCEN
ADC Select Data
Schmitt Trigger
To ADC
Figure 1-9. Pin Circuit Type E-4 (P0, P3)
Figure 1-11. Pin Circuit Type F-16 (P2.0-P2.3)
VLC0 VDD VLC1 Pull-up Enable Data Output Disable Circuit Type C P-Channel COM Out
I/O
Port Enable (PG2CON.4-5) Schmitt Trigger
VLC2
Figure 1-10. Pin Circuit Type D-7 (P1)
Figure 1-12. Pin Circuit Type H (COM0-COM3)
1-9
PRODUCT OVERVIEW
S3C830A/P830A
VLC0 VLC1
VDD
Pull-up Enable
SEG Output Disable VLC2 Out
Data Output Disable
Circuit Type C
I/O
Figure 1-13. Pin Circuit Type H-39
Figure 1-15. Pin Circuit Type D-4 (P2.4-P2.7)
VDD Pull-up Resistor Resistor Enable P-CH I/O N-CH
VDD Open Drain Data Output Disable1 SEG Output Disable2 Circuit Type H-39
Figure 1-14. Pin Circuit Type H-41 (P4-P8)
1-10
S3C830A/P830A
ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
The S3C830A microcontroller has two types of address space: -- Internal program memory (ROM) -- Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C830A has an internal 48-Kbyte mask-programmable ROM. The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes. A 20-byte LCD display register file is implemented. There are 2,134 mapped registers in the internal register file. Of these, 2,064 are for general-purpose. (This number includes a 16-byte working register common area used as a "scratch area" for data operations, eight 192-byte prime register areas, and eight 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the CPU and the system control, and 57 registers are mapped for peripheral controls and data registers. Ten register locations are not mapped.
2-1
ADDRESS SPACES
S3C830A/P830A
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C830A has 48K bytes internal maskprogrammable program memory. The first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. The ROM address at which a program execution starts after a reset is 0100H.
(Decimal) 49,151 48K-bytes Internal Program Memory Area
(HEX) BFFFH
255 Interrupt Vector Area 0
FFH
0H
Figure 2-1. Program Memory Address Space
2-2
S3C830A/P830A
ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3C830A implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3C830A the total number of addressable 8-bit registers is 2134. Of these 2134 registers, 13 bytes are for CPU and system control registers, 57 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 2048 registers are for general-purpose use, page 0-page 7 (including 20 bytes for LCD display registers). You can always address set 1 register locations, regardless of which of the eight register pages is currently selected. Set 1 locations, however, can only be addressed using register addressing modes. The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1. Table 2-1. S3C830A Register Type Summary Register Type General-purpose registers (including the 16-byte common working register area, eight 192-byte prime register area (including LCD data registers), and eight 64-byte set 2 area). CPU and system control registers Mapped clock, peripheral, I/O control, and data registers Total Addressable Bytes Number of Bytes 2,064
13 57 2,134
2-3
ADDRESS SPACES
S3C830A/P830A
FFH Set 1 FFH FFH 32 Bytes Bank 1 FFH FFH FFH
Page 7 Page 1 Page 0
Bank 0 System and Peripheral Control System and Registers Peripheral Control Registers (Register Addressing Mode) System Registers (Register Addressing Mode) Working Registers (Working Register Addressing Only)
Set 2 Registers (Indirect Register, Indexed Mode, and Stack Operations) 256 Bytes C0H BFH Page 0
64 Bytes
E0H DFH D0H CFH C0H
~ ~
~ Page 7 192 Bytes Prime Data Registers (All Addressing Modes) ~ ~
13H 20 Bytes 00H
~
~
~
Prime Data Registers (All Addressing Modes) LCD Display Register
~
00H
Figure 2-2. Internal Register File Organization
2-4
S3C830A/P830A
ADDRESS SPACES
REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C830A microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP) DFH ,Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Destination register page selection bits: 0000 Destination: Page 0
Source register page selection bits: 0000 Source: Page 0
NOTE:
A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should be modified to address other pages.
Figure 2-3. Register Page Pointer (PP)
+ PROGRAMMING TIP -- Using the Page Pointer for RAM clear (Page 0, Page 1)
LD SRP LD CLR DJNZ CLR LD LD CLR DJNZ CLR PP,#00H #0C0H R0,#0FFH @R0 R0,RAMCL0 @R0 PP,#10H R0,#0FFH @R0 R0,RAMCL1 @R0 ; Destination 0, Source 0 ; Page 0 RAM clear starts
RAMCL0
; R0 = 00H ; Destination 1, Source 0 ; Page 1 RAM clear starts
RAMCL1
; R0 = 00H
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
2-5
ADDRESS SPACES
S3C830A/P830A
REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H-FFH. The upper 32-byte area of this 64-byte space (E0H-FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H-FFH) contains 57 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H-DFH) and a 16-byte common working register area (C0H-CFH). You can use the common working register area as a "scratch" area for data operations being performed in other areas of the register file. Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, "Addressing Modes.") REGISTER SET 2 The same 64-byte physical space that is used for set 1 locations C0H-FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3C830A, the set 2 address range (C0H-FFH) is accessible on pages 0-7. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area of page 0 is commonly used for stack operations.
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S3C830A/P830A
ADDRESS SPACES
PRIME REGISTER SPACE The lower 192 bytes (00H-BFH) of the S3C830A's eight 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, 1, 2, 3, 4, 5, 6, or 7 you must set the register page pointer (PP) to the appropriate source and destination values.
FFH FFH FFH FFH FFH FFH Set 1 Bank 0 FFH FCH E0H D0H C0H C0H BFH Bank 1 FFH FFH
Page 7 Page 6
Page 5 Page 4
Page 3
Page 2 Set 2 Page 1 Set 2 Page 0 Set 2 C0H BFH Page 0 Set 2
Page 7 Page 0 Prime Space 13H LCD Data Register Area 00H
CPU and system control General-purpose Peripheral and I/O LCD data register 00H
Prime Space 00H
Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map
2-7
ADDRESS SPACES
S3C830A/P830A
WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers. Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except the set 2 area. The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: -- One working register slice is 8 bytes (eight 8-bit working registers, R0-R7 or R8-R15) -- One working register block is 16 bytes (sixteen 8-bit working registers, R0-R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H-CFH).
Slice 32 11111XXX RP1 (Registers R8-R15) Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block. Slice 31
FFH F8H F7H F0H Set 1 Only
CFH C0H
~
00000XXX RP0 (Registers R0-R7) Slice 2 Slice 1
~
10H FH 8H 7H 0H
Figure 2-5. 8-Byte Working Register Areas (Slices)
2-8
S3C830A/P830A
ADDRESS SPACES
USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H-C7H, and RP1 points to addresses C8H-CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-6 and 2-7). With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H-FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-6). In some cases, it may be necessary to define working register areas in different (noncontiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice. Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements.
+ PROGRAMMING TIP -- Setting the Register Pointers
SRP SRP1 SRP0 CLR LD #70H #48H #0A0H RP0 RP1,#0F8H ; ; ; ; ; RP0 RP0 RP0 RP0 RP0 70H, RP1 78H no change, RP1 48H, A0H, RP1 no change 00H, RP1 no change no change, RP1 0F8H
Register File Contains 32 8-Byte Slices 00001XXX RP1 00000XXX RP0 8-Byte Slice 8-Byte Slice
FH (R15) 8H 7H 0H (R0)
16-Byte Contiguous Working Register block
Figure 2-6. Contiguous 16-Byte Working Register Block
2-9
ADDRESS SPACES
S3C830A/P830A
8-Byte Slice
F7H (R7) F0H (R0)
11110 RP0 00000 RP1
XXX
Register File Contains 32 8-Byte Slices
16-Byte Contiguous working Register block 7H (R15) 0H (R0)
XXX
8-Byte Slice
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
+ PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H-85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively: SRP0 ADD ADC ADC ADC ADC #80H R0,R1 R0,R2 R0,R3 R0,R4 R0,R5 ; ; ; ; ; ; RP0 80H R0 R0 + R0 R0 + R0 R0 + R0 R0 + R0 R0 +
R1 R2 + C R3 + C R4 + C R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: ADD ADC ADC ADC ADC 80H,81H 80H,82H 80H,83H 80H,84H 80H,85H ; ; ; ; ; 80H 80H 80H 80H 80H (80H) (80H) (80H) (80H) (80H) + + + + + (81H) (82H) (83H) (84H) (85H)
+ + + +
C C C C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
2-10
S3C830A/P830A
ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space. Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB Rn
LSB Rn+1
n = Even address
Figure 2-8. 16-Bit Register Pair
2-11
ADDRESS SPACES
S3C830A/P830A
Special-Purpose Registers Bank 1 FFH Control Registers E0H D0H C0H BFH RP1 Register Pointers RP0 Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). NOTE: In the S3C830A microcontroller, pages 0-7 are implemented. Pages 0-7 contain all of the addressable registers in the internal register file. System Registers CFH Bank 0
General-Purpose Register
FFH
Set 2
C0H
Prime Registers
LCD Data Registers
00H
Page 0 Register Addressing Only All Addressing Modes
Page 0 Indirect Register, All Indexed Addressing Addressing Modes Modes Can be Pointed by register Pointer
Can be Pointed by Register Pointer
Figure 2-9. Register File Addressing
2-12
S3C830A/P830A
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H-CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H-CFH, as the active 16-byte working register block: RP0 C0H-C7H RP1 C8H-CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.
FFH FFH FFH FFH FFH FFH FFH Set 1 FFH FCH E0H D0H C0H C0H BFH Page 0 Prime Space FFH
Page 7 Page 6
Page 5 Page 4
Page 3
Page 2 Set 2 Page 1 Set 2 Page 0 Set C0H 2 BFH Page 0 Set 2
~ ~ ~ ~ ~ ~
00H 13H LCD Data Registers Page 7
Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH. RP0 = RP1 = 1100 1100 0000 1000 00H
~
Prime Space
~ ~
Figure 2-10. Common Working Register Area
2-13
ADDRESS SPACES
S3C830A/P830A
+ PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples 1. LD SRP LD 0C2H,40H #0C0H R2,40H ; Invalid addressing mode!
Use working register addressing instead: ; R2 (C2H) the value in location 40H
2. ADD 0C3H,#45H ; Invalid addressing mode! Use working register addressing instead: SRP ADD #0C0H R3,#45H ; R3 (C3H) R3 + 45H
4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: -- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1). -- The five high-order bits in the register pointer select an 8-byte slice of the register space. -- The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
2-14
S3C830A/P830A
ADDRESS SPACES
RP0 RP1 Selects RP0 or RP1 Address OPCODE
Register pointer provides five high-order bits
4-bit address provides three low-order bits
Together they create an 8-bit register address
Figure 2-11. 4-Bit Working Register Addressing
RP0 01110 000
RP1 01111 000
Selects RP0
01110
110
Register address (76H)
R6 0110
OPCODE 1110 Instruction 'INC R6'
Figure 2-12. 4-Bit Working Register Addressing Example
2-15
ADDRESS SPACES
S3C830A/P830A
8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing. As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B).
RP0 RP1 Selects RP0 or RP1 Address These address bits indicate 8-bit working register addressing 8-bit logical address
1
1
0
0
Register pointer provides five high-order bits
Three low-order bits
8-bit physical address
Figure 2-13. 8-Bit Working Register Addressing
2-16
S3C830A/P830A
ADDRESS SPACES
RP0 01100 000 Selects RP1
RP1 10101 000
R11 1100 1 011
8-bit address form instruction 'LD R11, R2'
10101
011
Register address (0ABH)
Specifies working register addressing
Figure 2-14. 8-Bit Working Register Addressing Example
2-17
ADDRESS SPACES
S3C830A/P830A
SYSTEM AND USER STACK
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C830A architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15.
High Address
PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt Low Address
Stack contents after a call instruction
Figure 2-15. Stack Operations User-Defined Stacks You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI, PUSHUD, POPUI, and POPUD support user-defined stack operations. Stack Pointers (SPL, SPH) Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The most significant byte of the SP address, SP15-SP8, is stored in the SPH register (D8H), and the least significant byte, SP7-SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C830A, the SPL must be initialized to an 8-bit value in the range 00H-FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary. When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H".
2-18
S3C830A/P830A
ADDRESS SPACES
+ PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine)
* * *
PUSH PUSH PUSH PUSH
* * *
PP RP0 RP1 R3
; ; ; ;
Stack address 0FEH Stack address 0FDH Stack address 0FCH Stack address 0FBH

PP RP0 RP1 R3
POP POP POP POP
R3 RP1 RP0 PP
; ; ; ;
R3 Stack address 0FBH RP1 Stack address 0FCH RP0 Stack address 0FDH PP Stack address 0FEH
2-19
ADDRESS SPACES
S3C830A/P830A
NOTES
2-20
S3C830A/P830A
ADDRESSING MODES
3
OVERVIEW
ADDRESSING MODES
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Indirect Address (IA) -- Relative Address (RA) -- Immediate (IM)
3-1
ADDRESSING MODES
S3C830A/P830A
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory 8-bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to One Register in Register File Value used in Instruction Execution
OPERAND
Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File MSB Point to RP0 or RP1
RP0 or RP1 Selected RP points to start of working register block OPERAND
Program Memory 4-bit Working Register Two-Operand Instruction (Example) 3 LSBs Point to the Working Register (1 of 8)
dst
src
OPCODE
Sample Instruction: ADD R1, R2 ; Where R1 and R2 are registers in the curruntly selected working register area.
Figure 3-2. Working Register Addressing
3-2
S3C830A/P830A
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H-FFH in set 1 using the Indirect Register addressing mode.
Program Memory 8-bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to One Register in Register File Address of Operand used by Instruction
ADDRESS
Value used in Instruction Execution
OPERAND
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
S3C830A/P830A
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Register Pair 16-Bit Address Points to Program Memory
dst OPCODE
Program Memory Sample Instructions: CALL JP @RR2 @RR2
Value used in Instruction
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
S3C830A/P830A
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1
RP0 or RP1 Selected RP points to start fo working register block
Program Memory 4-bit Working Register Address 3 LSBs Point to the Working Register (1 of 8)
~
~
dst
src
OPCODE
ADDRESS
~
Sample Instruction: OR R3, @R6 Value used in Instruction OPERAND
~
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C830A/P830A
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects Register Pair 16-Bit address points to program memory or data memory
Program Memory 4-bit Working Register Address dst src OPCODE
Example Instruction References either Program Memory or Data Memory
Program Memory or Data Memory
Value used in Instruction
OPERAND
Sample Instructions: LDC LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3C830A/P830A
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H-FFH in set 1 using Indexed addressing mode. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented.
Register File
RP0 or RP1
~
Value used in Instruction OPERAND
~
Selected RP points to start of working register block
+
Program Memory Two-Operand Instruction Example Base Address dst/src x OPCODE 3 LSBs Point to One of the Woking Register (1 of 8)
~
INDEX
~
Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C830A/P830A
INDEXED ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block
~
Program Memory 4-bit Working Register Address OFFSET dst/src x OPCODE NEXT 2 Bits Point to Working Register Pair (1 of 4) Register Pair
~
LSB Selects
+
8-Bits 16-Bits
Program Memory or Data Memory
16-Bit address added to offset
16-Bits Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + 04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C830A/P830A
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block
Program Memory OFFSET OFFSET dst/src src OPCODE
~
NEXT 2 Bits Point to Working Register Pair Register Pair
~
4-bit Working Register Address
LSB Selects
+
8-Bits 16-Bits
Program Memory or Data Memory
16-Bit address added to offset
16-Bits Sample Instructions: LDC LDE R4, #1000H[RR2] R4,#1000H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + 1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES
S3C830A/P830A
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE
LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Sample Instructions: LDC LDE R5,1234H R5,1234H ; ; The values in the program address (1234H) are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C830A/P830A
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Memory Address Used Upper Address Byte Lower Address Byte OPCODE
Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES
S3C830A/P830A
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode. Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero Current Instruction dst OPCODE
Lower Address Byte Upper Address Byte
Program Memory Locations 0-255
Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
3-12
S3C830A/P830A
ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current PC Value Signed Displacement Value
+
Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
Figure 3-13. Relative Addressing
3-13
ADDRESSING MODES
S3C830A/P830A
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
S3C830A/P830A
ELECTRICAL DATA
20
OVERVIEW
ELECTRICAL DATA
In this chapter, S3C830A electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Input/output capacitance -- Data retention supply voltage in stop mode -- A/D converter electrical characteristics -- PLL electrical characteristics -- Low voltage reset electrical characteristics -- Serial I/O timing characteristics -- Oscillation characteristics -- Oscillation stabilization time
20-1
ELECTRICAL DATA
S3C830A/P830A
Table 20-1. Absolute Maximum Ratings (TA= 25 C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO IOH IOL TA TSTG Conditions - Ports 0-8 - One I/O pin active All I/O pins active Output current low One I/O pin active Total pin current for port Operating temperature Storage temperature Rating - 0.3 to +6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 60 + 30 + 100 - 25 to + 85 - 65 to + 150
C
Unit V
mA
Table 20-2. D.C. Electrical Characteristics (TA = -25 C to + 85 C, VDD = 3.0 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions fx = 0.4-4.5 MHz (except PLL/IFC) fx = 4.5 MHz (PLL/IFC) Input high voltage VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 VOH2 Ports 0-8 RESET, CE XIN, XOUT Ports 0-8 RESET, CE XIN, XOUT VDD = 4.5 V to 5.5 V EO0, EO1; IOH = -1 mA VDD = 4.5 V to 5.5 V Other output ports; IOH = -1 mA VDD = 4.5 V to 5.5 V EO0, EO1; IOL = 1 mA VDD = 4.5 V to 5.5 V Other output ports; IOL = 10 mA VDD - 2.0 VDD - 1.0 - - - Min. 3.0 4.5 0.8 VDD 0.8 VDD VDD-0.1 - Typ. - - Max. 5.5 5.5 VDD VDD VDD 0.2 VDD 0.2 VDD 0.1 VDD VDD Unit V
Output low voltage
VOL1 VOL2
- - -
2.0 2.0
20-2
S3C830A/P830A
ELECTRICAL DATA
Table 20-2. D.C. Electrical Characteristics (Continued) (TA = -25 C to + 85 C, VDD = 3.0 V to 5.5 V) Parameter Input high leakage current Symbol ILIH1 Conditions VIN = VDD All input pins except XIN, XOUT VIN = VDD, XIN, XOUT VIN = 0 V All input pins except RESET, XIN, XOUT VIN = 0 V, XIN, XOUT VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V; VDD = 5 V Port 0-8 VIN = 0 V; VDD = 5 V; RESET Pull-down resistor RD VIN = VDD, VDD = 5 V VCOFM, VCOAM, AMIF and FMIF VDD = 5 V, TA = 25 C XIN = VDD, XOUT = 0 V TA = 25 C -15 A per common pin 15 35 45 k - - 25 150 - - 50 250 - - Min. - Typ. - Max. 3 Unit uA
ILIH2 Input low leakage current ILIL1
20 -3
ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RL1 RL2
-20 3 -3 100 400 k
Oscillator feed back resistors LCD voltage dividing resistor |VLCD - COMi| voltage drop (I = 0-3) |VLCD - SEGx| voltage drop (x = 0-39) Middle output voltage
ROSC RLCD VDC
300
750
1500
k
70 -
110 45
150 120
k mV
VDS
-15 A per common pin
-
45
120
mV
VLC0 VLC1 VLC2
VDD = 3.0 V to 5.5 V
0.6VDD- 0.2 0.4VDD- 0.2 0.2VDD- 0.2
0.6VDD 0.4VDD 0.2VDD
0.6VDD + 0.2 0.4VDD + 0.2 0.2VDD + 0.2
V
20-3
ELECTRICAL DATA
S3C830A/P830A
Table 20-2. D.C. Electrical Characteristics (Concluded) (TA = -25 C to + 85 C, VDD = 3.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Run mode: 4.5 MHz crystal oscillator CE = VDD VDD = 5 V 10 % C1 = C2 = 22pF Run mode: 4.5 MHz crystal oscillator CE = 0 V VDD = 5 V 10 % C1 = C2 = 22pF Idle mode: 4.5 MHz crystal oscillator VDD = 5 V 10 % Stop mode (in LVR disable): CE = 0 V, TA = 25 C VDD = 5 V 10 % Min. - Typ. 5.0 Max. 15 Unit mA
IDD2
-
2.6
5.5
IDD3
-
0.6
2.0
IDD4 (2)
-
0.5
3
A
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, PWM, or external output current loads. 2. IDD4 is current when the main clock oscillation stops. 3. Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.
20-4
S3C830A/P830A
ELECTRICAL DATA
Table 20-3. A.C. Electrical Characteristics (TA = -25 C to +85 C, VDD = 3.0 V to 5.5 V) Parameter Interrupt input high, low width (P1.0-P1.7) RESET input low width Symbol tINTH, tINTL tRSL Conditions P1.0-P1.7, VDD = 5 V Min 200 Typ - Max Unit ns
VDD = 5 V
10
-
-
us
tTIL
tTIH
0.8 VDD 0.2 VDD 0.2 VDD
Figure 20-1. Input Timing for External Interrupts (Ports 1)
tRSL
RESET
0.2 V DD
Figure 20-2. Input Timing for RESET
20-5
ELECTRICAL DATA
S3C830A/P830A
Table 20-4. Input/Output Capacitance (TA = -25 C to +85 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are returned to VSS Min - Typ - Max 10 Unit pF
Table 20-5. Data Retention Supply Voltage in Stop Mode (TA = -25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR = 2 V (TA = 25 C) Stop mode (in LVR disable) Conditions Min 3.0 - Typ - - Max 5.5 1 Unit V uA
RESET Occurs
Stop Mode Data Retention Mode
Oscillation Stabilization Time Normal Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction RESET 0.2 VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fxx tWAIT
Figure 20-3. Stop Mode Release Timing Initiated by RESET
20-6
S3C830A/P830A
ELECTRICAL DATA
Oscillation Stabilization Time Stop Mode Data Retention Mode Idle Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instruction Interrupt 0.2 VDD tWAIT
Normal Operating Mode
NOTE:
tWAIT is the same as 16 x 1/BT clock
Figure 20-4. Stop Mode Release Timing Initiated by Interrupts
Table 20-6. A/D Converter Electrical Characteristics (TA = -25 C to +85 C, VDD = 3.5 V to 5.5 V, VSS = 0 V) Parameter A/D converting resolution Absolute accuracy A/D conversion time Analog input voltage Analog input impedance Symbol - - tCON VIAN RAN VDD = 5 V Conditions - - Conversion clock = fxx - Min - - 50/fxx VSS 2 - 1000 Typ 8 - Max - 2 - VDD - Unit bits LSB s V M
20-7
ELECTRICAL DATA
S3C830A/P830A
Table 20-7. PLL Electrical Characteristics (TA = -25 C to +85 C, VDD = 4.5 V to 5.5 V) Parameter VCOFM, VCOAM, FMIF and AMIF input voltage (peak to peak) Frequency Symbol VIN Conditions Sine wave input Min 0.3 Typ - Max VDD Unit V
fVCOAM fVCOFM f AMIF f FMIF
VCOAM mode, sine wave input; VIN = 0.3VP-P VCOFM mode, sine wave input; VIN = 0.3VP-P AMIF mode, sine wave input; VIN = 0.3VP-P FMIF mode, sine wave input; VIN = 0.3VP-P
0.5 30 0.1 5
-
30 150 1.0 15
MHz
Table 20-8. Low Voltage Reset Electrical Characteristics (TA = -25 C to +85 C) Parameter Detect voltage range LVR operating current Symbol VDET IBL - Conditions Min 3.0 - Typ 3.5 10 Max 4.0 25 Unit V A
20-8
S3C830A/P830A
ELECTRICAL DATA
Table 20-9. Synchronous SIO Electrical Characteristics (TA = -25 C to +85 C, VDD = 3.0 V to 5.5 V) Parameter SCK0/SCK1 cycle time Symbol tCKY tKH, tKL Conditions External SCK0/SCK1 source Internal SCK0/SCK1 source SCK0/SCK1 high, low width SI setup time to SCK0/SCK1 high SI hold time to SCK0/SCK1 high Output delay for SCK0/SCK1 to SO tKSO tKSI tSIK External SCK0/SCK1 source Internal SCK0/SCK1 source External SCK0/SCK1 source Internal SCK0/SCK1 source External SCK0/SCK1 source Internal SCK0/SCK1 source External SCK0/SCK1 source Internal SCK0/SCK1 source Min 1000 1000 500 tKCY/2- 50 250 250 400 400 - - 300 250 - - - - - - Typ - Max - Unit ns
tCKY tKL SCK0/SCK1 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD Input Data 0.2 VDD tKH
SI0/SI1
tKSO SO0/SO1 Output Data
Figure 20-5. Serial Data Transfer Timing
20-9
ELECTRICAL DATA
S3C830A/P830A
Table 20-10. Main Oscillator Characteristics (fx) (TA = -25 C to +85 C, VDD = 3.0 V to 5.5 V) Oscillator Crystal Clock Circuit
XIN XOUT
Test Condition Crystal oscillation frequency
Min 0.4
Typ -
Max 4.5
Unit MHz
C1
C2
Ceramic
XIN
XOUT
Ceramic oscillation frequency
0.4
-
4.5
MHz
C1
C2
External clock
XIN
XOUT
XIN input frequency
0.4
-
4.5
MHz
Table 20-11. Main Oscillator Clock Stabilization Time (tST1) (TA = -25 C to +85 C, VDD = 3.0 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 4.5 V to 5.5 V Stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low level width (tXH, tXL) Min - - 111 Typ - - - Max 10 4 1250 Unit ms ms ns
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore be held at low level until the tST1 time has elapsed
20-10
S3C830A/P830A
ELECTRICAL DATA
1/fx tXL XIN VDD-0.1V 0.1V tXH
Figure 20-6. Clock Timing Measurement at XIN
Instruction Clock 1.125 MHZ
Main Oscillator Frequency 4.5 MHZ
25 kHz 1 2 3 4 5 6 7
400 kHz
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16) When PLL/IFC operation, operating voltage range is 4.5 V to 5.5 V.
Figure 20-7. Operating Voltage Range
20-11
ELECTRICAL DATA
S3C830A/P830A
NOTES
20-12
S3C830A/P830A
MECHANICAL DATA
21
OVERVIEW
MECHANICAL DATA
The S3C830A microcontroller is currently available in 100-pin-QFP package.
23.90 0.30 20.00 0.20 0-8
+ 0.10
0.15 - 0.05
17.90 0.30
14.00 0.20
100-QFP-1420C
0.10 MAX
(0.83)
#100
#1 0.65
0.30
+ 0.10 - 0.05
0.15 MAX
0.05 MIN (0.58) 2.65 0.10 3.00 MAX
0.10 MAX 0.80 0.20 NOTE: Dimensions are in millimeters.
Figure 21-1. Package Dimensions (100-QFP-1420C)
0.80 0.20
21-1
MECHANICAL DATA
S3C830A/P830A
NOTES
21-2
S3C830A/P830A
S3P830A OTP
22
OVERVIEW
S3P830A OTP
The S3P830A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C830A microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P830A is fully compatible with the S3C830A, both in function in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the S3P830A is ideal as an evaluation chip for the S3C830A.
22-1
S3P830A OTP
S3C830A/P830A
FMIF VDDPLL0 EO0 EO1 CE P0.0 P0.1/T0CLK P0.2/T0CAP P0.3/T0OUT/T0PWM P0.4/T1CLK P0.5/T1OUT P0.6/T2CLK P0.7/T2OUT P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
P1.7/INT7 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4 P2.5 P2.6 P2.7 AVDD P3.0/BUZ P3.1/SCK0 SDAT/P3.2/SO0 SCLK/P3.3/SI0 VDD/VDD VSS/VSS XOUT XIN VPP/TEST1 TEST2 P3.4/SCK1 RESET/RESET RESET P3.5/SO1 P3.6/SI1 P3.7 P4.0/SEG39 P4.1/SEG38 P4.2/SEG37 P4.3/SEG36 P4.4/SEG35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3P830A
100-QFP-1420C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
AMIF VSSPLL VCOAM VCOFM VDDPLL1 LVREN TEST3 BIAS VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 SEG0/P8.7 SEG1/P8.6 SEG2/P8.5 SEG3/P8.4 SEG4/P8.3 SEG5/P8.2 SEG6/P8.1 SEG7/P8.0 SEG8/P7.7 SEG9/P7.6 SEG10/P7.5 SEG11/P7.4 SEG12/P7.3 SEG13/P7.2 SEG14/P7.1
Figure 22-1. S3P830A Pin Assignments (100-Pin QFP Package)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG15/P7.0 SEG16/P6.7 SEG17/P6.6 SEG18/P6.5 SEG19/P6.4 SEG20/P6.3 SEG21/P6.2 SEG22/P6.1 SEG23/P6.0 SEG24/P5.7 SEG25/P5.6 SEG26/P5.5 SEG27/P5.4 SEG28/P5.3 SEG29/P5.2 SEG30/P5.1 SEG31/P5.0 SEG32/P4.7 SEG33/P4.6 SEG34/P4.5
22-2
S3C830A/P830A
S3P830A OTP
Table 22-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P3.2/SO0 Pin Name SDAT Pin No. 13 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P3.3/SI0 TEST1
SCLK VPP
14 19
I I
RESET VDD/VSS
RESET VDD/VSS
22 15/16
I -
Table 22-2. Comparison of S3P830A and S3C830A Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 3.0 V to 5.5 V VDD = 5 V, VPP (TEST1) = 12.5 V 100 QFP User Program 1 time 100 QFP Programmed at the factory S3P830A 48-Kbyte EPROM S3C830A 48-Kbyte mask ROM 3.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST1) pin of the S3P830A, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 22-3. Operating Mode Selection Criteria VDD 5V VPP (TEST1) 5V 12.5 V 12.5 V 12.5 V REG/MEM MEM 0 0 0 1 Address(A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 Mode EPROM read EPROM program EPROM verify EPROM read protection
NOTE: "0" means Low level; "1" means High level.
22-3
S3P830A OTP
S3C830A/P830A
Instruction Clock 1.125 MHZ
Main Oscillator Frequency 4.5 MHZ
25 kHz 1 2 3 4 5 6 7
400 kHz
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16) When PLL/IFC operation, operating voltage range is 4.5 V to 5.5 V.
Figure 22-2. Operating Voltage Range
22-4

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